CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumers. Today, multi-media applications generally require at least 64 MB memory of memory and, preferably, 128 MB of memory. Such memory requirements increase the relative cost of the memory system within a computer. In the near future, it is likely that 256 MB and 512 MB computers will become commonplace, which suggests a potentially strong demand for 256 Mb Dynamic Random Access Memories (DRAMs) and those of a larger capacity. The creation of DRAMs in the gigabit range is already under way; however, such high-density DRAMs are still in the development stage. As DRAM density and lithographic difficulties increase, the testing of memory cells in a semiconductor memory becomes a more critical element in the development and production of DRAMs.
FIG. 1 is a dynamic random access memory (DRAM) 100 having a typical structure according to the prior art. The DRAM 100 includes a first array 102n+1, a second array 102n, and a third array 102n-1. Each array contains a plurality of memory cells arranged in a matrix. Each memory cell consists of an NMOS transistor 110 and a capacitor C.sub.S. A memory cell holds a data bit as a capacitive charge voltage in capacitor C.sub.S. The read or write operation of the data bit is controlled by a wordline WL. The horizontally running WL is coupled to the gates of a plurality of the NMOS transistors 110. When the WL rises, the corresponding NMOS transistor 110 couples the corresponding capacitor C.sub.S to a bitline BL, allowing the data bit in the capacitor C.sub.S to be accessed through the bitline BL. Each vertically running bitline BL is coupled to the drains of a plurality of the NMOS transistors 110, thereby supporting a plurality of the memory cells (i.e. 256 for 256 Mb DRAM).
For the sake of simplicity, the capacitance of a bitline is modeled as a capacitor C.sub.BL. When the wordline WL rises, the charge of the capacitor C.sub.S is shared with the charge of the capacitor C.sub.BL, changing a bitline voltage (sensing voltage). The following discussion presumes that the capacitor C.sub.S stores a supply voltage (Vdd) or 0V, and that the bitline BL is originally precharged to 2Vdd. The sensing signal is thus determined by .+-.2Vdd(C.sub.S /(C.sub.S +C.sub.BL)). Typically, capacitor C.sub.S and capacitor C.sub.BL are about 30 fF and 120 fF, respectively. For Vdd=2V, the sensing signal=200 mV. Each bitline pair (BL and BL) is supported by a corresponding sense amplifier SA. When sense amplifier SA is turned ON, the sensing signal of 200 mV is amplified, making the bitline BL and the bitline BL go HIGH and LOW, respectively (or vice versa). The HIGH and LOW voltage levels of the bitlines are the complimentary metal-oxide semiconductor (CMOS) voltage levels (either 0V or Vdd) after the corresponding sense amplifier SA has amplified the sensing signal.
For high density DRAMs, such as 256 Mb DRAMs and greater, a sense amplifier SA is shared between an array located above the sense amplifier and another array located below the sense amplifier. This is a common approach to reduce the number of sense amplifiers SAs and, thus, reduce the DRAM chip size. To relax the layout pitch of the sense amplifiers SAs, the sense amplifiers SAs are arranged in an alternating manner.
The accessing of memory cell data bits in the second array 102n will now be described with respect to FIGS. 1 and 2. FIG. 2 is a timing diagram illustrating the state of some of the signals of the DRAM 100 of FIG. 1 during an access operation of memory cell data bits. In a standby state, the bitlines BLs are equalized by an NMOS transistor 144 and precharged at 1/2VDD level. MUXn+1b, MUXnt, MUXnb, and MUXn-1t are bitline multiplexer control signals, where n indicates the which array, and t and b indicate the top or the bottom of that array, respectively. In a standby condition, all bitline multiplexer control signals (i.e. MUXn+1b, MUXnt, MUXnb, and MUXn-1t) are HIGH. Accordingly, the nodes SA and SA in the sense amplifier SA are coupled to the bitlines BL and BL, respectively, in the second array 102n through bitline multiplexer NMOS transistor pair 132, 134. Further, the nodes SA and SA in the sense amplifier SA are coupled to the bitlines BL and BL, respectively, in the third array 102n-1 through bitline multiplexer NMOS transistor pair 136, 138.
When the second array 102n is activated, the equalizer signal EQ goes LOW. To isolate the bitlines BLs in the first and third arrays (102n+1 and 102n-1, respectively) from the bitlines BLs in the second array 102n, the bitline multiplexer control signals MUXn+1b and MUXn-1t go LOW, while any other bitline multiplexer control signals, including MUXnt and MUXnb, remain HIGH. This is because only the multiplexers adjacent to the accessed array need be controlled. All other multiplexers (including those for arrays not shown) may be placed in a standby state, by putting their bitline multiplexer control signals HIGH.
A wordline WL in the second array 102n then rises, and a data bit in the corresponding capacitor C.sub.S is read out to the corresponding bitline BL in the second array 102n through the corresponding NMOS transistor 110 coupled to the wordline WL. A CMOS cross-coupled sense amplifier SA (comprised of NMOS transistors 128 and 130 and PMOS transistors 120 and 122) is then activated. More particularly, the NMOS sense amplifier enable signal NSA and the PMOS sense amplifier enable signal PSA go HIGH and LOW, respectively. This makes the NMOS transistor 150 and the PMOS transistor 124 turn ON, amplifying the voltage of each bitline pair.
The column select line signal CSL rises, coupling the selected BL pair to the data line pair (DL and DL) through the column switch NMOS transistors (140 and 142). In this example, the column select line signal CSL remains LOW. The amplified voltage on the bitlines BLs are written back to the capacitor C.sub.S of the corresponding memory cells. In a reset phase, the equalizer signal EQ, and the bitline multiplexer control signals MUXn+1b and MUXn-1t go HIGH, equalizing all the bitlines BLs. This naturally precharges the bitlines BLs at the 2Vdd level in a standby state.
Correct operation of the DRAM is strongly dependent upon a reliable sensing operation. Nonetheless, there are several factors that cause sensing failures. Some of these factors include: (1) a small cell capacitance C.sub.S ; (2) a large bitline capacitance C.sub.BL ; (3) capacitance mismatch of a bitline pair; (4) threshold voltage mismatch of the cross-coupled devices; and (5) bitline-to-bitline coupling noise.
Accordingly, there is a need for a method and apparatus which determines the sensing margin of the sense amplifiers SAs in a semiconductor memory. The sensing margin is the minimum detectable voltage difference that a sense amplifier can detect (its sensitivity). Moreover, there is a need for a method and apparatus which identifies existing problems in semiconductor memories. Further, there is a need for a method and apparatus which enables the testing of semiconductor memories.